What, no 10gb/s Snort On A Chip?

Thomas Ptacek | June 29th, 2005 | Filed Under: Uncategorized

Interesting Cell/Xenon scoop on Slashdot today:

Not to mention that the requirements for hitting peak theoretical performance are always ridiculous; caches are only so big and thus there will come a time where a request to main memory is needed, and you can expect that request to be fulfilled in a few hundred clock cycles, where no floating point operations will be happening at all.

Ahhh, memory performance. Great equalizer, righter of wrongs. How will you work your wiles on the Octeon? The 1450? The Raza XLR?

Of course, it’s also necessary to reconcile this new “multicore will not take over the world as planned” meme with what Cringely said a few months back. You mean I can’t go get a 10MM round by launching the industry’s “first Cell-based network IPS”? Or did Symbiot already try that?